diff options
| author | Hou Zhiqiang <[email protected]> | 2022-03-11 17:49:35 -0600 |
|---|---|---|
| committer | Lorenzo Pieralisi <[email protected]> | 2022-04-08 12:35:21 +0100 |
| commit | 6c389328c985a3aa8575cf3a573a05c1d121fceb (patch) | |
| tree | 861dda0d823ca1b32d0e0341e8fbed127c39f54a | |
| parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) | |
dt-bindings: pci: layerscape-pci: Add a optional property big-endian
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Rob Herring <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f36efa73a470..215d2ee65c83 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -40,6 +40,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { |