diff options
| author | AngeloGioacchino Del Regno <[email protected]> | 2021-07-29 00:25:15 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2021-08-04 15:07:03 -0500 |
| commit | 6bb717fe56f67218715fd3b8eaf65bb1fe8f8458 (patch) | |
| tree | a16a3df29354305d0182748d3038361f055748bd | |
| parent | a64fa0e23b5f712828379319d20b32546e0cfb94 (diff) | |
arm64: dts: qcom: sdm630: Add clocks and power domains to SMMU nodes
Add the required clocks and power domains for the SMMUs to work.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm630.dtsi | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3c94d892083d..108e9e1ba28e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -563,9 +563,14 @@ anoc2_smmu: iommu@16c0000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x016c0000 0x40000>; - #iommu-cells = <1>; + assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; + assigned-clock-rates = <1000>; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; + clock-names = "bus"; #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, @@ -904,9 +909,22 @@ kgsl_smmu: iommu@5040000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x05040000 0x10000>; - #iommu-cells = <1>; + /* + * GX GDSC parent is CX. We need to bring up CX for SMMU + * but we need both up for Adreno. On the other hand, we + * need to manage the GX rpmpd domain in the adreno driver. + * Enable CX/GX GDSCs here so that we can manage just the GX + * RPM Power Domain in the Adreno driver. + */ + power-domains = <&gpucc GPU_GX_GDSC>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_GPU_BIMC_GFX_CLK>; + clock-names = "iface", "mem", "mem_iface"; #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, @@ -1597,9 +1615,16 @@ mmss_smmu: iommu@cd00000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>; - #iommu-cells = <1>; + clocks = <&mmcc MNOC_AHB_CLK>, + <&mmcc BIMC_SMMU_AHB_CLK>, + <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, + <&mmcc BIMC_SMMU_AXI_CLK>; + clock-names = "iface-mm", "iface-smmu", + "bus-mm", "bus-smmu"; #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, |