diff options
| author | Gustavo Sousa <[email protected]> | 2023-08-14 10:13:30 -0300 |
|---|---|---|
| committer | Matt Roper <[email protected]> | 2023-08-17 12:25:14 -0700 |
| commit | 6a62986bb52e3c96372d92486f9461190144a66b (patch) | |
| tree | 005c64fe5f19d890afd8dbe6d71e3b17475d4770 | |
| parent | 0f5c2e5bd2fc8d2e09043b6bb3c81a889a483997 (diff) | |
drm/i915/cx0: Enable/disable TX only for owned PHY lanes
Display must not enable or disable transmitters for not-owned PHY lanes.
BSpec: 64539
Reviewed-by: Mika Kahola <[email protected]>
Signed-off-by: Gustavo Sousa <[email protected]>
Signed-off-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 2b112ed78943..93d3a63fe89a 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2607,10 +2607,11 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, int i; u8 disables; bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder); enum port port = encoder->port; if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, + intel_cx0_rmw(i915, port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); @@ -2625,11 +2626,13 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); } - /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */ for (i = 0; i < 4; i++) { int tx = i % 2 + 1; u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; + if (!(owned_lane_mask & lane_mask)) + continue; + intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2), CONTROL2_DISABLE_SINGLE_TX, disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, @@ -2637,7 +2640,7 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, } if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, + intel_cx0_rmw(i915, port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); |