diff options
| author | Mauro Lima <[email protected]> | 2022-10-12 12:21:35 -0300 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2022-10-13 13:01:37 +0100 |
| commit | 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 (patch) | |
| tree | aefb6073741de020f21d9d039982cc7442659276 | |
| parent | 5302e1ff315b40dfc9bb3f08911f5a788cc1de01 (diff) | |
spi: intel: Fix the offset to get the 64K erase opcode
According to documentation, the 64K erase opcode is located in VSCC
range [16:23] instead of [8:15].
Use the proper value to shift the mask over the correct range.
Signed-off-by: Mauro Lima <[email protected]>
Reviewed-by: Mika Westerberg <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
| -rw-r--r-- | drivers/spi/spi-intel.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index 55f4ee2db002..605acb1bf4b0 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -114,7 +114,7 @@ #define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_SHIFT 16 -#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) +#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) /* Flash descriptor fields */ #define FLVALSIG_MAGIC 0x0ff0a55a |