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authorEzequiel Garcia <[email protected]>2018-03-28 18:00:55 -0300
committerUlf Hansson <[email protected]>2018-05-02 15:08:35 +0200
commit671963bbb3a72211960662e9ac274c1fb9e08234 (patch)
tree483b0bac90b442a13bed7baf93fb19a11ab73835
parent7f5a07f4c2d22cf9a07a1a959cd5561795c8d527 (diff)
MIPS: dts: ci20: Enable MMC in the devicetree
Now that we have support for JZ480 SoCs in the MMC driver, let's enable it on the devicetree. Acked-by: James Hogan <[email protected]> Tested-by: Mathieu Malaterre <[email protected]> Signed-off-by: Ezequiel Garcia <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
-rw-r--r--arch/mips/boot/dts/ingenic/ci20.dts34
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 38078594cf97..50cff3cbcc6d 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -36,6 +36,28 @@
clock-frequency = <48000000>;
};
+&mmc0 {
+ status = "okay";
+
+ bus-width = <4>;
+ max-frequency = <50000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_mmc0>;
+
+ cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
+};
+
+&mmc1 {
+ status = "okay";
+
+ bus-width = <4>;
+ max-frequency = <50000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_mmc1>;
+};
+
&uart0 {
status = "okay";
@@ -203,4 +225,16 @@
groups = "nemc-cs6";
bias-disable;
};
+
+ pins_mmc0: mmc0 {
+ function = "mmc0";
+ groups = "mmc0-1bit-e", "mmc0-4bit-e";
+ bias-disable;
+ };
+
+ pins_mmc1: mmc1 {
+ function = "mmc1";
+ groups = "mmc1-1bit-d", "mmc1-4bit-d";
+ bias-disable;
+ };
};