diff options
| author | Manivannan Sadhasivam <[email protected]> | 2024-03-21 16:46:40 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2024-04-21 12:28:49 -0500 |
| commit | 669841a2eff4c0132841dea3ae40d9148a36f257 (patch) | |
| tree | c48def33b09b890ca98bd55d157fb344a56564ab | |
| parent | 27cb9eccf94cb163f9bf3b945f249ab7c42861db (diff) | |
ARM: dts: qcom: sdx55: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index edc9aaf828c8..68fa5859d263 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -378,6 +378,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie_ep: pcie-ep@1c00000 { |