diff options
| author | Konrad Dybcio <[email protected]> | 2023-05-17 04:18:50 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-05-24 21:11:28 -0700 |
| commit | 661a4f089317c877aecd598fb70cd46510cc8d29 (patch) | |
| tree | a329d3f5a444b2804558306d9f7dba65fdf7b4bb | |
| parent | 3a735530c159b75e1402c08abe1ba4eb99a1f7a3 (diff) | |
arm64: dts: qcom: sm8550: Use the correct LLCC register scheme
During the ABI-breaking (for good reasons) conversion of the LLCC
register description, SM8550 was not taken into account, resulting
in LLCC being broken on any kernel containing the patch referenced
in the fixes tag.
Fix it by describing the regions properly.
Fixes: ee13b5008707 ("qcom: llcc/edac: Fix the base address used for accessing LLCC banks")
Signed-off-by: Konrad Dybcio <[email protected]>
Acked-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 4c6b2c582b27..558cbc430708 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3771,9 +3771,16 @@ system-cache-controller@25000000 { compatible = "qcom,sm8550-llcc"; - reg = <0 0x25000000 0 0x800000>, + reg = <0 0x25000000 0 0x200000>, + <0 0x25200000 0 0x200000>, + <0 0x25400000 0 0x200000>, + <0 0x25600000 0 0x200000>, <0 0x25800000 0 0x200000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; }; |