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authorLucas De Marchi <[email protected]>2023-10-24 15:04:12 -0700
committerRodrigo Vivi <[email protected]>2023-12-21 11:43:26 -0500
commit65e95735882329632559cf71c9efbb4981473b07 (patch)
tree54e29bcecb0b0856dbba0e9ce6725ae514bd7fa8
parentbfeb4ac55565f527f72e97020a244f8c3585154a (diff)
drm/xe: Fix WA 14010918519 write to wrong register
FORCE_SLM_FENCE_SCOPE_TO_TILE and FORCE_UGM_FENCE_SCOPE_TO_TILE are in the up dword of LSC_CHICKEN_BIT_0 register. Also, the 14010918519 workaround only applies to early steppings, A*. Eventually those should be dropped, like they were in commit eaeb4b361452 ("drm/i915/dg2: Drop pre-production GT workarounds"), so let's make sure they are annotated appropriately. Reviewed-by: Gustavo Sousa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
-rw-r--r--drivers/gpu/drm/xe/xe_wa.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index ccb075aac7da..ce61609b001c 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -367,9 +367,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
},
{ XE_RTP_NAME("14010918519"),
- XE_RTP_RULES(SUBPLATFORM(DG2, G10),
+ XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
FUNC(xe_rtp_match_first_render_or_compute)),
- XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0,
+ XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
FORCE_SLM_FENCE_SCOPE_TO_TILE |
FORCE_UGM_FENCE_SCOPE_TO_TILE,
/*