diff options
| author | Chris Park <[email protected]> | 2022-01-05 23:39:56 -0500 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-01-18 17:43:36 -0500 |
| commit | 6421c49567d55b1ba8d9389e5832297398a51a1c (patch) | |
| tree | 0f8827ca2eb74e3bd67faa621fd819fc6a12984e | |
| parent | c1a20f707ac33b1fec1d78bab74e07656c237801 (diff) | |
drm/amd/display: DCEFCLK DS on CLK init
[Why]
On HG APU + dGPU scenario with no display to dGPU,
DS stays disabled due to no display present.
This problem can be worked around by DAL calling
DCEFCLK DS message to SMU on clk init.
[How]
Call DCEFCLK DS message to SMU on clk init.
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Wayne Lin <[email protected]>
Signed-off-by: Chris Park <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index f977f29907df..0602bde78e6c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -184,6 +184,7 @@ void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK, &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, &num_levels); + dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, 0); /* DTBCLK */ dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK, |