diff options
| author | Paul Burton <[email protected]> | 2016-05-17 15:31:04 +0100 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2016-05-28 12:35:02 +0200 |
| commit | 640356a48750ff9ef3303d85158ef9c42c3a18b6 (patch) | |
| tree | 156b010b5d2c78df6048993a9dd6284f17bf65d7 | |
| parent | 6e4ad1b413604b9130bdbe532aafdbd47ff5318e (diff) | |
MIPS: Clear Status IPL field when using EIC
When using an external interrupt controller (EIC) the interrupt mask
bits in the cop0 Status register are reused for the Interrupt Priority
Level, and any interrupts with a priority lower than the field will be
ignored. Clear the field to 0 by default such that all interrupts are
serviced. Without doing so we default to arbitrarily ignoring all or
some subset of interrupts.
Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Matt Redfearn <[email protected]>
Tested-by: Matt Redfearn <[email protected]>
Cc: Guenter Roeck <[email protected]>
Cc: Sergei Shtylyov <[email protected]>
Cc: Joe Perches <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/13272/
Signed-off-by: Ralf Baechle <[email protected]>
| -rw-r--r-- | arch/mips/kernel/irq.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 8eb5af805964..f25f7eab7307 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -54,6 +54,9 @@ void __init init_IRQ(void) for (i = 0; i < NR_IRQS; i++) irq_set_noprobe(i); + if (cpu_has_veic) + clear_c0_status(ST0_IM); + arch_init_irq(); } |