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authorKonrad Dybcio <[email protected]>2023-07-03 20:20:12 +0200
committerBjorn Andersson <[email protected]>2023-08-13 19:52:09 -0700
commit63f4e4b447c50ba7e5fc3929644d2d152acb6117 (patch)
tree63f469ad5e4f8a50ef80ab67f215d7a78666564b
parent00ada6afea88006187b38bd96b6d1b7d8e3d90cb (diff)
arm64: dts: qcom: msm8998: Use the correct GPLL0_DIV leg for MMCC
MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. We've already been using the correct one in the non-div case, start doing so for the other one as well. Reviewed-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
-rw-r--r--arch/arm64/boot/dts/qcom/msm8998.dtsi6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 4605dd3a942d..3f0a13bdc323 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2724,7 +2724,8 @@
"dsi1byte",
"hdmipll",
"dplink",
- "dpvco";
+ "dpvco",
+ "gpll0_div";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_MMSS_GPLL0_CLK>,
<0>,
@@ -2733,7 +2734,8 @@
<0>,
<0>,
<0>,
- <0>;
+ <0>,
+ <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
};
mmss_smmu: iommu@cd00000 {