diff options
| author | Xingyu Wu <[email protected]> | 2023-05-09 23:17:23 +0800 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-05-15 17:44:38 +0100 |
| commit | 6361b7de262aca8704abfaade5166a940f7cc571 (patch) | |
| tree | 511ecf48304ef8a71ac42fa4187d14cdf5d39fd4 | |
| parent | 435ac3fbfbc64a4557862a612058383748a3c7f0 (diff) | |
riscv: dts: starfive: jh7110: Add watchdog node
Add the watchdog node for the Starfive JH7110 SoC.
Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Walker Chen <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 30e1f34d5cf8..03c6cc49fa22 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -469,6 +469,16 @@ #gpio-cells = <2>; }; + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>; |