diff options
| author | Yu Chien Peter Lin <[email protected]> | 2024-02-22 16:39:44 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2024-03-12 07:13:17 -0700 |
| commit | 61609bf2b29dcb07de3aaad7d6212cc3c341192b (patch) | |
| tree | 1fcb8da15dfd401dede7a27584e48be67b57848e | |
| parent | bc969d6cc96a2d0539576ec639f7a2a7dcf757f8 (diff) | |
dt-bindings: riscv: Add Andes PMU extension description
Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/extensions.yaml | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..468c646247aa 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -477,5 +477,12 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter overflow + and privilege mode filtering. For more details, see Counter Related + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + additionalProperties: true ... |