diff options
| author | Will Deacon <[email protected]> | 2012-01-20 12:10:18 +0100 |
|---|---|---|
| committer | Russell King <[email protected]> | 2012-01-23 10:20:06 +0000 |
| commit | 612539e81f655f6ac73c7af1da8701c1ee618aee (patch) | |
| tree | a442b17625ad28e282c4ddb0f786ccdfbe4f8bf4 | |
| parent | 868dbf905245a524496a0535982ed21ad3be5585 (diff) | |
ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards
On v7, we use the same cache maintenance instructions for data lines
as for unified lines. This was not the case for v6, where HARVARD_CACHE
was defined to indicate the L1 cache topology.
This patch removes the erroneous compile-time check for HARVARD_CACHE in
proc-v7.S, ensuring that we perform I-side invalidation at boot.
Reported-and-Acked-by: Shawn Guo <[email protected]>
Cc: stable <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b15597400105..0404ccbb8aa3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume) * Initialise TLB, Caches, and MMU state ready to switch the MMU * on. Return in r0 the new CP15 C1 control register setting. * - * We automatically detect if we have a Harvard cache, and use the - * Harvard cache control instructions insead of the unified cache - * control instructions. - * * This should be able to cover all ARMv7 cores. * * It is assumed that: @@ -251,9 +247,7 @@ __v7_setup: #endif 3: mov r10, #0 -#ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate -#endif dsb #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |