diff options
| author | Frederik Haxel <[email protected]> | 2023-12-12 14:01:13 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2024-01-09 19:33:21 -0800 |
| commit | 5daa3726410288075ba73c336bb2e80d6b06aa4d (patch) | |
| tree | a1451f18f991c636ba19215a0a5ae7c4c3da52e1 | |
| parent | 66f1e68093979816a23412a3fad066f5bcbc0360 (diff) | |
riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro
During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.
Fixes: bee7fbc38579 ("RISC-V CPU Idle Support")
Fixes: e7681beba992 ("RISC-V: Split out the XIP fixups into their own file")
Signed-off-by: Frederik Haxel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
| -rw-r--r-- | arch/riscv/include/asm/xip_fixup.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/xip_fixup.h b/arch/riscv/include/asm/xip_fixup.h index d4ffc3c37649..b65bf6306f69 100644 --- a/arch/riscv/include/asm/xip_fixup.h +++ b/arch/riscv/include/asm/xip_fixup.h @@ -13,7 +13,7 @@ add \reg, \reg, t0 .endm .macro XIP_FIXUP_FLASH_OFFSET reg - la t1, __data_loc + la t0, __data_loc REG_L t1, _xip_phys_offset sub \reg, \reg, t1 add \reg, \reg, t0 |