diff options
| author | Lars Povlsen <[email protected]> | 2021-02-03 13:38:25 +0100 |
|---|---|---|
| committer | Linus Walleij <[email protected]> | 2021-03-10 14:41:24 +0100 |
| commit | 5d5f2919273d1089a00556cad68e7f462f3dd2eb (patch) | |
| tree | ad818e132baf90008ef85d0b712552c2d11d1e59 | |
| parent | a38fd8748464831584a19438cbb3082b5a2dab15 (diff) | |
pinctrl: microchip-sgpio: Fix wrong register offset for IRQ trigger
This patch fixes using a wrong register offset when configuring an IRQ
trigger type.
Fixes: be2dc859abd4 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)")
Reported-by: Gustavo A. R. Silva <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
Reviewed-by: Gustavo A. R. Silva <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
| -rw-r--r-- | drivers/pinctrl/pinctrl-microchip-sgpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index f35edb0eac40..c12fa57ebd12 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -572,7 +572,7 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, /* Type value spread over 2 registers sets: low, high bit */ sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, BIT(addr.port), (!!(type & 0x1)) << addr.port); - sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit, + sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, BIT(addr.port), (!!(type & 0x2)) << addr.port); if (type == SGPIO_INT_TRG_LEVEL) |