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authorAtish Patra <[email protected]>2024-04-20 08:17:18 -0700
committerAnup Patel <[email protected]>2024-04-22 11:13:44 +0530
commit5d4acb7f2e1af1a5160870dbd11d2bd3a86007ed (patch)
tree46f81525558551582ccfc7696eaf3e8ff7931939
parentd1927f64e0e1094f296842e127138cb5f3bf3c6d (diff)
RISC-V: Add FIRMWARE_READ_HI definition
SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Reviewed-by: Andrew Jones <[email protected]> Reviewed-by: Clément Léger <[email protected]> Acked-by: Conor Dooley <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Reviewed-by: Anup Patel <[email protected]> Signed-off-by: Atish Patra <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
-rw-r--r--arch/riscv/include/asm/sbi.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 6e68f8dff76b..ef8311dafb91 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid {
SBI_EXT_PMU_COUNTER_START,
SBI_EXT_PMU_COUNTER_STOP,
SBI_EXT_PMU_COUNTER_FW_READ,
+ SBI_EXT_PMU_COUNTER_FW_READ_HI,
};
union sbi_pmu_ctr_info {