diff options
| author | Rohit Agarwal <[email protected]> | 2023-05-18 23:17:50 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-05-30 07:54:18 -0700 |
| commit | 57b60d03d5a682d366a4850b1f69c53fc13beb22 (patch) | |
| tree | 758d5a7f3c3049bf5852864b6451a3e0344bf813 | |
| parent | d2f1bd8f0b91ce77951d983a094c157b2efd789c (diff) | |
ARM: dts: qcom: sdx65: Add support for PCIe PHY
Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
used by the PCIe EP controller.
Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx65.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 525dd8a1f664..2fe61c296e39 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -295,6 +295,37 @@ status = "disabled"; }; + pcie_phy: phy@1c06000 { + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; + reg = <0x01c06000 0x2000>; + + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; |