diff options
| author | Dhinakaran Pandiyan <[email protected]> | 2019-12-21 14:05:38 +0200 |
|---|---|---|
| committer | Imre Deak <[email protected]> | 2019-12-23 13:50:56 +0200 |
| commit | 55656505dc55481d862b7ff81aba69a002e39159 (patch) | |
| tree | 469e0b330a741f957ab4da4005d9f42980d3cd69 | |
| parent | e7af9094579474912ac7ea2d2f2434c4df2fd5e6 (diff) | |
drm/framebuffer: Format modifier for Intel Gen-12 render compression
Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä <[email protected]>
Cc: Matt Roper <[email protected]>
Cc: Nanley G Chery <[email protected]>
Cc: Jason Ekstrand <[email protected]>
Cc: Mika Kahola <[email protected]>
Cc: [email protected]
Signed-off-by: Dhinakaran Pandiyan <[email protected]>
Signed-off-by: Lucas De Marchi <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Reviewed-by: Mika Kahola <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | include/uapi/drm/drm_fourcc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 8caaaf7ff91b..5ba481f49931 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -411,6 +411,17 @@ extern "C" { #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) /* + * Intel color control surfaces (CCS) for Gen-12 render compression. + * + * The main surface is Y-tiled and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * Y-tile widths. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) + +/* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * * Macroblocks are laid in a Z-shape, and each pixel data is following the |