diff options
| author | Abhilash Kesavan <[email protected]> | 2014-10-17 21:42:53 +0530 |
|---|---|---|
| committer | Wim Van Sebroeck <[email protected]> | 2014-12-05 20:21:35 +0100 |
| commit | 5476b2b77dae50c88aa6a85f21abeac38dde590f (patch) | |
| tree | bbd810f8db7cf313fa9fff899c3f09262853ae5d | |
| parent | 56c67ce187a899f76c5f22dd30fd9cfc3d95a0c2 (diff) | |
watchdog: s3c2410_wdt: Fix the mask bit offset for Exynos7
The watchdog mask bit offset listed for Exynos7 is incorrect.
Fix this.
Signed-off-by: Abhilash Kesavan <[email protected]>
Acked-by: Naveen Krishna Chatradhi <[email protected]
Reviewd-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
| -rw-r--r-- | drivers/watchdog/s3c2410_wdt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 8532c3e2aea7..1626dc66e763 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -161,7 +161,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = { static const struct s3c2410_wdt_variant drv_data_exynos7 = { .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, - .mask_bit = 0, + .mask_bit = 23, .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, .rst_stat_bit = 23, /* A57 WDTRESET */ .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, |