diff options
| author | Piyush Mehta <[email protected]> | 2022-12-09 14:54:47 +0100 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2023-01-05 09:53:33 +0100 |
| commit | 53ba1b2bdaf7f481fdd878e9c18cd0e54081fac9 (patch) | |
| tree | f6feb5118785e267106e2b82acd5f0d176e2cc58 | |
| parent | 32405e532d358a2f9d4befae928b9883c8597616 (diff) | |
arm64: dts: zynqmp: Add mode-pin GPIO controller DT node
Add mode-pin GPIO controller DT node in zynqmp.dtsi and wire it to usb0
controller. All Xilinx evaluation boards are using modepin gpio for ULPI
reset that's why wire it directly in zynqmp instead of c&p the same line to
every board specific file.
Signed-off-by: Piyush Mehta <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/69924a8e2c01e5a1d25d098adc53224ddb841f46.1670594085.git.michal.simek@amd.com
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 130df216fa1b..9793a4e652d9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -13,6 +13,7 @@ */ #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> @@ -199,6 +200,12 @@ compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; + + modepin_gpio: gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; }; }; @@ -847,6 +854,7 @@ <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { |