diff options
| author | Ville Syrjälä <[email protected]> | 2023-06-09 17:13:52 +0300 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2023-06-16 17:54:13 +0300 |
| commit | 5197c49d20e39ee5dd60df2272ae6fe6cf7ebfe9 (patch) | |
| tree | e09c5183bd1d1743e1e0e0c07d731a7701ee4040 | |
| parent | d4b62a1a251db33a453ffa9d3535bf6f4a011546 (diff) | |
drm/i915: Re-init clock gating on coming out of PC8+
PC8+ clobbers a bunch of displays registers which need to
be restored by hand or else we lost a bunch of workarounds.
The important ones for us are at least CHICKEN_PAR2* and
CHICKEN_PIPESL*.
Curiously at least some CHICKEN_PAR1* registers
are preserved by the hardware/firmware. Unfortunately Bspec
doens't really specify what gets clobbered vs. preserved
so further reverse engieering might be warranted to figure
out the specifics.
Note that PCH_LP_PARTITION_LEVEL_DISABLE is also set by
lpt_init_clock_gating() so the rmw in hsw_disable_pc8()
is now redundant. Remove it.
TODO: I suspect most gt stuff doesn't need this and we should
finish moving all of them from init_clock_gating() to
a more appropriate place...
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jouni Högander <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index db5437043904..d3310c720532 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -10,6 +10,7 @@ #include "i915_reg.h" #include "intel_backlight_regs.h" #include "intel_cdclk.h" +#include "intel_clock_gating.h" #include "intel_combo_phy.h" #include "intel_de.h" #include "intel_display_power.h" @@ -1385,9 +1386,8 @@ static void hsw_disable_pc8(struct drm_i915_private *dev_priv) hsw_restore_lcpll(dev_priv); intel_init_pch_refclk(dev_priv); - if (HAS_PCH_LPT_LP(dev_priv)) - intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, - 0, PCH_LP_PARTITION_LEVEL_DISABLE); + /* Many display registers don't survive PC8+ */ + intel_clock_gating_init(dev_priv); } static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, |