diff options
| author | Madhumitha Tolakanahalli Pradeep <[email protected]> | 2023-04-18 15:04:45 -0700 |
|---|---|---|
| committer | Radhakrishna Sripada <[email protected]> | 2023-04-19 15:33:32 -0700 |
| commit | 514b8a79aa85d800458cfb7909ed0e1a1c1bffa2 (patch) | |
| tree | bfc097b9183824ee235200b8fe9bfc5facc2ad78 | |
| parent | 0c29efa23f5c2f51b744856200af0cff3e287e9e (diff) | |
drm/i915/mtl: Extend Wa_22011802037 to MTL A-step
Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch
updates the if statement to apply the W/A to right platforms and extends
it to MTL-M:A step.
v1.1: Fix checkpatch warning.
v2: Change the check to reflect the wa at other places(Lucas)
Bspec: 66622
Cc: Lucas De Marchi <[email protected]>
Cc: Umesh Nerlige Ramappa <[email protected]>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <[email protected]>
Signed-off-by: Radhakrishna Sripada <[email protected]>
Reviewed-by: Matt Atwood <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 88e881b100cf..ee3e8352637f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1629,16 +1629,16 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub) static void guc_engine_reset_prepare(struct intel_engine_cs *engine) { - if (!IS_GRAPHICS_VER(engine->i915, 11, 12)) - return; - - intel_engine_stop_cs(engine); - /* * Wa_22011802037: In addition to stopping the cs, we need * to wait for any pending mi force wakeups */ - intel_engine_wait_for_pending_mi_fw(engine); + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) || + (GRAPHICS_VER(engine->i915) >= 11 && + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) { + intel_engine_stop_cs(engine); + intel_engine_wait_for_pending_mi_fw(engine); + } } static void guc_reset_nop(struct intel_engine_cs *engine) |