diff options
| author | Daniel Vetter <[email protected]> | 2013-04-19 11:14:35 +0200 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2013-04-25 21:21:50 +0200 |
| commit | 4f4134ace04fd5b0e8734b65f4046e7aa2e39393 (patch) | |
| tree | bf1a84fcac3f7f4b4120f5b7d8421f824dfb13a7 | |
| parent | d8b322474941fa565ba5c58292ccc54be92cca41 (diff) | |
drm/i915: don't force matching p1 for g4x/ilk+ reduced pll settings
g4x dplls and ilk+ pch plls have a separate field for the reduced p1
setting, so this restriction does not apply. Only older platforms have
the restriction that the p1 divisors must match.
This unnecessary restriction has been introduced in
commit cec2f356d59d9e070413e5966a3c5a1af136d948
Author: Sean Paul <[email protected]>
Date: Tue Jan 10 15:09:36 2012 -0800
drm/i915: Only look for matching clocks for LVDS downcloc
Note that with lvds the p2 divisors _always_ match for LVDS, and we
don't support auto-downclocking anywhere else. On eDP downclocking
works with separate data m/n settings, using the same link clock.
Cc: Sean Paul <[email protected]>
Reviewed-by: Sean Paul <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 38465f0e9710..fa9af52ba5a4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -685,9 +685,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, if (!intel_PLL_is_valid(dev, limit, &clock)) continue; - if (match_clock && - clock.p != match_clock->p) - continue; this_err = abs(clock.dot - target); if (this_err < err_most) { |