diff options
| author | Paul Kocialkowski <[email protected]> | 2020-08-03 11:06:58 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2020-09-01 14:13:27 +0200 |
| commit | 4c85f628f6639e3e3e0a7788416154f28dfcae4f (patch) | |
| tree | abc4f7ee479fd359af15d7316ed91a03dae96383 | |
| parent | 9eb88a819f43feed0743411317e569e836f6e4f1 (diff) | |
media: ov5640: Correct Bit Div register in clock tree diagram
Although the code is correct and doing the right thing, the clock diagram
showed the wrong register for the bit divider, which had me doubting the
understanding of the tree. Fix this to avoid doubts in the future.
Signed-off-by: Paul Kocialkowski <[email protected]>
Fixes: aa2882481cada ("media: ov5640: Adjust the clock based on the expected rate")
Acked-by: Jacopo Mondi <[email protected]>
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
| -rw-r--r-- | drivers/media/i2c/ov5640.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index ccdabc7948a7..637687d761f2 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -751,7 +751,7 @@ static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg, * +->| PLL Root Div | - reg 0x3037, bit 4 * +-+------------+ * | +---------+ - * +->| Bit Div | - reg 0x3035, bits 0-3 + * +->| Bit Div | - reg 0x3034, bits 0-3 * +-+-------+ * | +-------------+ * +->| SCLK Div | - reg 0x3108, bits 0-1 |