diff options
| author | Fenghua Yu <[email protected]> | 2016-10-22 06:19:51 -0700 |
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2016-10-26 23:12:38 +0200 |
| commit | 4ab1586488cb56ed8728e54c4157cc38646874d9 (patch) | |
| tree | e11da9a77f2d2f66930a06792124ac8af1d6475e | |
| parent | d57e3ab7e34c51a8badeea1b500bfb738d0af66e (diff) | |
x86/cpufeature: Add RDT CPUID feature bits
Check CPUID leaves for all the Resource Director Technology (RDT)
Cache Allocation Technology (CAT) bits.
Presence of allocation features:
CPUID.(EAX=7H, ECX=0):EBX[bit 15] X86_FEATURE_RDT_A
L2 and L3 caches are each separately enabled:
CPUID.(EAX=10H, ECX=0):EBX[bit 1] X86_FEATURE_CAT_L3
CPUID.(EAX=10H, ECX=0):EBX[bit 2] X86_FEATURE_CAT_L2
L3 cache may support independent control of allocation for
code and data (CDP = Code/Data Prioritization):
CPUID.(EAX=10H, ECX=1):ECX[bit 2] X86_FEATURE_CDP_L3
[ tglx: Fixed up Borislavs comments and moved the feature bits into a gap ]
Signed-off-by: Fenghua Yu <[email protected]>
Acked-by: "Borislav Petkov" <[email protected]>
Cc: "Ravi V Shankar" <[email protected]>
Cc: "Tony Luck" <[email protected]>
Cc: "David Carrillo-Cisneros" <[email protected]>
Cc: "Sai Prakhya" <[email protected]>
Cc: "Peter Zijlstra" <[email protected]>
Cc: "Stephane Eranian" <[email protected]>
Cc: "Dave Hansen" <[email protected]>
Cc: "Shaohua Li" <[email protected]>
Cc: "Nilay Vaish" <[email protected]>
Cc: "Vikas Shivappa" <[email protected]>
Cc: "Ingo Molnar" <[email protected]>
Cc: "H. Peter Anvin" <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Thomas Gleixner <[email protected]>
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 4 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/scattered.c | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index a39629206864..90b8c0b185c3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -189,6 +189,9 @@ #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ +#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ +#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ +#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ @@ -221,6 +224,7 @@ #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ +#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 1db8dc490b66..49fb680bb0e5 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -36,6 +36,9 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) { X86_FEATURE_AVX512_4FMAPS, CR_EDX, 3, 0x00000007, 0 }, { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 }, { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, + { X86_FEATURE_CAT_L3, CR_EBX, 1, 0x00000010, 0 }, + { X86_FEATURE_CAT_L2, CR_EBX, 2, 0x00000010, 0 }, + { X86_FEATURE_CDP_L3, CR_ECX, 2, 0x00000010, 1 }, { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 }, |