diff options
| author | Serge Semin <[email protected]> | 2022-11-13 22:12:53 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <[email protected]> | 2022-11-23 16:01:55 +0100 |
| commit | 4a8972542a6d1eee81c7cc27699b0a47f6a6619e (patch) | |
| tree | f5e75a275a13174f34901570287521a48a86e809 | |
| parent | bd9504af9169131156e753a6e47de34ad7a97b7d (diff) | |
dt-bindings: PCI: dwc: Add dma-coherent property
DW PCIe EP/RP AXI- and TRGT1-master interfaces are responsible for the
application memory access. They are used by the RP/EP PCIe buses (MWr/MWr
TLPs emitted by the peripheral PCIe devices) and the eDMA block. Since all
of them mainly involve the system memory and basically mean DMA we can
expect the corresponding platforms can be designed in a way to make sure
the transactions are cache-coherent. As such the DW PCIe DT-nodes can have
the 'dma-coherent' property specified. Let's permit it in the DT-bindings
then.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Serge Semin <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml index 4d9efcea3859..d87e13496834 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml @@ -259,6 +259,8 @@ properties: configuration space registers, Port Logic registers, DMA and iATU registers. This feature has been available since DWC PCIe v4.80a. + dma-coherent: true + additionalProperties: true ... |