diff options
| author | Bhavya Kapoor <[email protected]> | 2023-12-01 13:50:44 +0530 |
|---|---|---|
| committer | Nishanth Menon <[email protected]> | 2023-12-15 10:05:58 -0600 |
| commit | 4a52a8208568a85b0d51e5ca81be5925973ef108 (patch) | |
| tree | fb503d5b88899ba41b8727ae2fc8a317dfe05fab | |
| parent | 908999561b4340089896b89cef51dae07fc001cb (diff) | |
arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD High Speed DDR which is DDR50 speed mode for J721s2 SoC
according to datasheet for J721s2.
[+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
J721s2 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf
Signed-off-by: Bhavya Kapoor <[email protected]>
Reviewed-by: Judith Mendez <[email protected]>
Reviewed-by: Udit Kumar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index bf959312fad0..ea7f2b2ab165 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -766,6 +766,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; |