diff options
| author | Phil Edworthy <[email protected]> | 2022-05-03 12:55:48 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-05-05 12:10:53 +0200 |
| commit | 4a526957e6368597dea08175a67f0e15569f3958 (patch) | |
| tree | 3f343f1cbae940d6c8f159a633af9e7ec7b878e8 | |
| parent | 049bddcb893141503923bf0dfc518136269c0a24 (diff) | |
dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 311a93590597..8880b834f264 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -4,14 +4,15 @@ $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode +title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode maintainers: - Geert Uytterhoeven <[email protected]> description: | On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module - Standby Mode share the same register block. + Standby Mode share the same register block. On RZ/V2M, the functionality is + similar, but does not have Clock Monitor Registers. They provide the following functionalities: - The CPG block generates various core clocks, @@ -26,6 +27,7 @@ properties: - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a09g011-cpg # RZ/V2M reg: maxItems: 1 @@ -43,9 +45,10 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - <dt-bindings/clock/r9a07g*-cpg.h> + <dt-bindings/clock/r9a0*-cpg.h> - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>. + a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or + <dt-bindings/clock/r9a09g011-cpg.h>. const: 2 '#power-domain-cells': @@ -59,7 +62,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the <dt-bindings/clock/r9a07g0*-cpg.h>. + the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>. const: 1 required: |