diff options
| author | Geert Uytterhoeven <[email protected]> | 2024-07-22 13:50:21 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2024-07-30 10:44:18 +0200 |
| commit | 4897930debb4abb98317b4a18c4f20bad1f71b9f (patch) | |
| tree | 9b095c58b9c275e85b08580f1be4bcf14e8a7ac4 | |
| parent | 354e5cf4f6ed8c25b3dbdffa14c1afaea21452c5 (diff) | |
clk: renesas: rcar-gen4: Removed unused SSMODE_* definitions
All SSMODE operations are done using CPG_PLLxCR0_SSMODE*.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/19f84bfec94eab5f301a9c33563c285ab59b9b2a.1721648548.git.geert+renesas@glider.be
| -rw-r--r-- | drivers/clk/renesas/rcar-gen4-cpg.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index 77a4bb3e17f3..72c740f18ac9 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -53,10 +53,6 @@ static u32 cpg_mode __initdata; #define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */ #define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */ -#define SSMODE_FM BIT(2) /* Fractional Multiplication */ -#define SSMODE_DITHER BIT(1) /* Frequency Dithering */ -#define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */ - /* PLL Clocks */ struct cpg_pll_clk { struct clk_hw hw; |