diff options
author | Lewis Huang <[email protected]> | 2021-04-09 18:39:43 +0800 |
---|---|---|
committer | Alex Deucher <[email protected]> | 2021-04-28 23:35:50 -0400 |
commit | 47c02af751d168372d6ba3189799671eab606ef1 (patch) | |
tree | 6dfa3815a6ef1a0693e0264f38ac8c5bf039e857 | |
parent | d5433a9f692f57c814286f8af2746c567ef79fc8 (diff) |
drm/amd/display: skip program clock when allow seamless boot
[Why]
Driver program dpp clock calculate by pipe split config but hw config is single pipe.
[How]
Skip programming clock when allow seamless boot.
After porgramming pipe config, seamless boot flag will be clear.
Signed-off-by: Lewis Huang <[email protected]>
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Wayne Lin <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index f4374d83662a..931fbb4d6169 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1206,14 +1206,25 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) { const struct dc *dc = link->dc; bool ret; + bool can_apply_seamless_boot = false; + int i; + + for (i = 0; i < dc->current_state->stream_count; i++) { + if (dc->current_state->streams[i]->apply_seamless_boot_optimization) { + can_apply_seamless_boot = true; + break; + } + } /* get out of low power state */ - clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); + if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT) + clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); ret = dc_link_detect_helper(link, reason); /* Go back to power optimized state */ - clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); + if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT) + clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); return ret; } |