diff options
| author | Pooya Keshavarzi <[email protected]> | 2016-04-19 08:29:55 +0200 |
|---|---|---|
| committer | Simon Horman <[email protected]> | 2016-05-30 09:34:49 +0900 |
| commit | 457f47b7651ccb1828c1d02f7ace0d07e9b16f33 (patch) | |
| tree | 1a40be51409c5b358b7a43737852f4b549dda81e | |
| parent | 3cac478cce564c11f56f30bd16530c2757b3e4f3 (diff) | |
arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
There are some requirements about the GIC-400 memory layout and its
mapping if using 64k aligned base addresses like on r8a7795.
See e.g.
http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=21550029f709072aacf3b9
Map the whole memory range instead of only 0x2000. This will fix
the issue that some hypervisors, e.g. Xen, fail to handle the
interrupts correctly.
Signed-off-by: Pooya Keshavarzi <[email protected]>
Signed-off-by: Dirk Behme <[email protected]>
Acked-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 3285a9286786..de3e799a7bba 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -157,9 +157,9 @@ #address-cells = <0>; interrupt-controller; reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x2000>, + <0x0 0xf1020000 0 0x20000>, <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x2000>; + <0x0 0xf1060000 0 0x20000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; |