diff options
| author | AngeloGioacchino Del Regno <[email protected]> | 2024-05-27 11:39:05 +0200 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <[email protected]> | 2024-06-27 10:10:25 +0200 |
| commit | 45682a4fffdd9abd6e2df9c5c534d22f2eda94f9 (patch) | |
| tree | e6285ec2732e00d43c512af4d30e06fd8943c479 | |
| parent | b220332f9849e82b55d566a40f9c8457b177e232 (diff) | |
arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes
In preparation for adding multimedia nodes and power domains, add
support for the two Global Command Engine (GCE) mailboxes found in
this SoC.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8188.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index b4315c9214dc..06fa3b862c31 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/mediatek,mt8188-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/mailbox/mediatek,mt8188-gce.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> #include <dt-bindings/power/mediatek,mt8188-power.h> @@ -413,6 +414,22 @@ clock-names = "spi", "wrap"; }; + gce0: mailbox@10320000 { + compatible = "mediatek,mt8188-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + }; + + gce1: mailbox@10330000 { + compatible = "mediatek,mt8188-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8188-scp"; reg = <0 0x10500000 0 0x100000>, |