diff options
| author | Eric Yang <[email protected]> | 2019-11-15 12:04:25 -0500 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-12-05 18:23:04 -0500 |
| commit | 44ce6c3dc8479bb3ed68df13b502b0901675e7d6 (patch) | |
| tree | 45979ce66d0ea9908ce127875dd62ff3e61d781b | |
| parent | dd0b162fd00915728860a360c97752988782b8cc (diff) | |
drm/amd/display: update dispclk and dppclk vco frequency
Value obtained from DV is not allowing 8k60 CTA mode with DSC to
pass, after checking real value being used in hw, find out that
correct value is 3600, which will allow that mode.
Signed-off-by: Eric Yang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index 6d99b4760695..c28cb5d50cf4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -257,7 +257,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { .vmm_page_size_bytes = 4096, .dram_clock_change_latency_us = 23.84, .return_bus_width_bytes = 64, - .dispclk_dppclk_vco_speed_mhz = 3550, + .dispclk_dppclk_vco_speed_mhz = 3600, .xfc_bus_transport_time_us = 4, .xfc_xbuf_latency_tolerance_us = 4, .use_urgent_burst_bw = 1, |