diff options
| author | Rob Herring <[email protected]> | 2020-08-20 21:54:15 -0600 |
|---|---|---|
| committer | Lorenzo Pieralisi <[email protected]> | 2020-09-10 16:50:53 +0100 |
| commit | 441e48fdf0b403218805b320d93de5caeafdcb1d (patch) | |
| tree | 76bbe68dec65d50ac790ab216ca13671f59c86f2 | |
| parent | 39bc5006501cc31987f4fc249c5ce07286b84768 (diff) | |
PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code
The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The
default value is set and it seems pretty certain that enabling link
initialization is always required. Maybe it could just be dropped from
the Intel driver, but lets move setting it into the common code to be
sure.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Dilip Kota <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.c | 1 | ||||
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-intel-gw.c | 4 |
2 files changed, 1 insertions, 4 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 62a6735ada9e..5240153c15ba 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -551,6 +551,7 @@ void dw_pcie_setup(struct dw_pcie *pci) val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_FAST_LINK_MODE; + val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); of_property_read_u32(np, "num-lanes", &pci->num_lanes); diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c index 2c0d32ffb828..d15e49b8df2a 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -164,10 +164,6 @@ static void intel_pcie_port_logic_setup(struct intel_pcie_port *lpp) val = FIELD_PREP(PORT_AFR_N_FTS_MASK, lpp->n_fts) | FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, lpp->n_fts); pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_AFR, mask, val); - - /* Port Link Control Register */ - pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_LINK_CONTROL, PORT_LINK_DLL_LINK_EN, - PORT_LINK_DLL_LINK_EN); } static void intel_pcie_rc_setup(struct intel_pcie_port *lpp) |