aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGregory CLEMENT <[email protected]>2017-06-09 12:09:17 +0200
committerLinus Walleij <[email protected]>2017-06-16 11:15:20 +0200
commit43a2dcecd8ae16c76026d6728e072a6c0aa2d8ac (patch)
treec7c95e8a14b401bca3934a8a0b2aa9bda3a05d16
parent3638bd4a066c14256bad0b99a60821709d3807b4 (diff)
gpio: mvebu: fix regmap_update_bits usage
In some place in the driver regmap_update_bits was misused. Indeed the last argument is not the value of the bit (or group of bits) itself but the mask value inside the register. So when setting the bit N, then the value must be BIT(N) and not 1. CC: Ralph Sennhauser <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]> Reviewed-by: Thomas Petazzoni <[email protected]> Tested-by: Ralph Sennhauser <[email protected]> Tested-by: Chris Packham <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
-rw-r--r--drivers/gpio/gpio-mvebu.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 3d03740a20e7..877a3edffa47 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -341,7 +341,7 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
return ret;
regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
- BIT(pin), 1);
+ BIT(pin), BIT(pin));
return 0;
}
@@ -503,7 +503,7 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW:
regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
- BIT(pin), 1);
+ BIT(pin), BIT(pin));
break;
case IRQ_TYPE_EDGE_BOTH: {
u32 data_in, in_pol, val;