diff options
author | Om Prakash Singh <[email protected]> | 2021-06-23 15:35:22 +0530 |
---|---|---|
committer | Lorenzo Pieralisi <[email protected]> | 2021-08-04 12:28:17 +0100 |
commit | 43537cf7e351264a1f05ed42ad402942bfc9140e (patch) | |
tree | b01b2a577fb4487a58c26eef8680c4d1aef77f11 | |
parent | ceb1412c1c8ca5b28c4252bdb15f2f1f17b4a1b0 (diff) |
PCI: tegra194: Fix MSI-X programming
Lower order MSI-X address is programmed in MSIX_ADDR_MATCH_HIGH_OFF
DBI register instead of higher order address. This patch fixes this
programming mistake.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Om Prakash Singh <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Bjorn Helgaas <[email protected]>
Acked-by: Vidya Sagar <[email protected]>
-rw-r--r-- | drivers/pci/controller/dwc/pcie-tegra194.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index fd14e2f45bba..55c8afb9a899 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1763,7 +1763,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); val |= MSIX_ADDR_MATCH_LOW_OFF_EN; dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val); - val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); + val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val); ret = dw_pcie_ep_init_complete(ep); |