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authorMiquel Raynal <[email protected]>2022-05-13 12:49:56 +0200
committerMiquel Raynal <[email protected]>2022-05-16 18:36:19 +0200
commit431cbce8495551ff433c9a4225afbf8ea5270d23 (patch)
treebd6bb28e394be0e8160caeea7c593da77d56f086
parent5794465b6fcfbaed304c8ebe8990f858eb2ed9a2 (diff)
dt-bindings: mtd: renesas: Fix the NAND controller description
Add the missing power-domain property which is needed on all the RZ/N1 SoC IPs. Suggested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/linux-mtd/[email protected]
-rw-r--r--Documentation/devicetree/bindings/mtd/renesas-nandc.yaml5
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml b/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
index 2870d36361c4..7b18bc5cc8b3 100644
--- a/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
+++ b/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
@@ -36,11 +36,15 @@ properties:
- const: hclk
- const: eclk
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
- clocks
- clock-names
+ - power-domains
- interrupts
unevaluatedProperties: false
@@ -56,6 +60,7 @@ examples:
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
clock-names = "hclk", "eclk";
+ power-domains = <&sysctrl>;
#address-cells = <1>;
#size-cells = <0>;
};