diff options
| author | Bryan O'Donoghue <[email protected]> | 2019-06-26 11:27:31 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2019-06-26 20:26:47 +0800 |
| commit | 4112c8537f07aad84c00841a5a30f4acfbbc8242 (patch) | |
| tree | 31c7898b3de26f3075585b51871d0f9c7004ecda | |
| parent | 159dbaf57b2f4f67ecb59b2c87d071e45ed41d7e (diff) | |
nvmem: imx-ocotp: Add i.MX8MM support
This patch adds support to burn the fuses on the i.MX8MM.
https://www.nxp.com/webapp/Download?colCode=IMX8MMRM
The i.MX8MM is similar to i.MX6 processors in terms of addressing and clock
setup.
The documentation specifies 60 discreet OTP registers but, the fusemap
address space encompasses up to 256 registers. We map the entire putative
256 OTP registers.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
| -rw-r--r-- | drivers/nvmem/imx-ocotp.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index b7dacf53c715..340ab336f987 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -473,6 +473,12 @@ static const struct ocotp_params imx8mq_params = { .set_timing = imx_ocotp_set_imx7_timing, }; +static const struct ocotp_params imx8mm_params = { + .nregs = 256, + .bank_address_words = 0, + .set_timing = imx_ocotp_set_imx6_timing, +}; + static const struct of_device_id imx_ocotp_dt_ids[] = { { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params }, { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params }, @@ -483,6 +489,7 @@ static const struct of_device_id imx_ocotp_dt_ids[] = { { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params }, { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params }, { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params }, + { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params }, { }, }; MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids); |