diff options
| author | Gregory CLEMENT <[email protected]> | 2012-09-26 18:02:50 +0200 |
|---|---|---|
| committer | Jason Cooper <[email protected]> | 2012-11-27 15:35:43 +0000 |
| commit | 3ee11aef75db51c69cb8cb91dd01afb28036f1b5 (patch) | |
| tree | 1926827b53f9d8043385921c56ba80b750a7646d | |
| parent | 2f96fbb7d851740d0594a6b74142083d51483ab5 (diff) | |
arm: l2x0: add aurora related properties to OF binding
Aurora is a L2 Cache Controller designed to be compatible with the
L2x0 Cache Controller. L2X0 OF bindings are extended to support some
specificity of Aurora (no cache id part number available through
hardware, always write through mode, choice between outer cache and
system cache).
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Yehuda Yitschak <[email protected]>
Tested-and-reviewed-by: Lior Amsalem <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Russell King <[email protected]>
Cc: Barry Song <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Olof Johansson <[email protected]>
Signed-off-by: Jason Cooper <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/l2cc.txt | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index 7ca52161e7ab..76b0ee6ee9a4 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -10,6 +10,12 @@ Required properties: "arm,pl310-cache" "arm,l220-cache" "arm,l210-cache" + "marvell,aurora-system-cache": Marvell Controller designed to be + compatible with the ARM one, with system cache mode (meaning + maintenance operations on L1 are broadcasted to the L2 and L2 + performs the same operation). + "marvell,"aurora-outer-cache: Marvell Controller designed to be + compatible with the ARM one with outer cache mode. - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped @@ -29,6 +35,9 @@ Optional properties: filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. - interrupts : 1 combined interrupt. +- cache-id-part: cache id part number to be used if it is not present + on hardware +- wt-override: If present then L2 is forced to Write through mode Example: |