diff options
| author | Wang Fudong <[email protected]> | 2022-08-17 17:47:50 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-08-30 17:00:21 -0400 |
| commit | 3e834a17a22cb8e9169c0b018d1a2df126977db3 (patch) | |
| tree | 839c4f172a72a2df9e1463af52f75a7b293443cb | |
| parent | 3c93603d9568c7c4b20ff1712ddc60e997d78df7 (diff) | |
drm/amd/display: set dig fifo read start level to 7 before dig fifo reset
[Why]
DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black.
[How]
We need to set dig fifo read start level = 7 before dig fifo reset during dig
fifo enable according to hardware designer's suggestion. If it is zero, it will
cause underflow or overflow and DIG_FIFO_ERROR = 1.
Reviewed-by: Alvin Lee <[email protected]>
Reviewed-by: Aric Cyr <[email protected]>
Acked-by: Brian Chang <[email protected]>
Signed-off-by: Wang Fudong <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c index 26648ce772da..38a48983f663 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -310,6 +310,11 @@ static void enc32_stream_encoder_dp_unblank( // TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000); + /* read start level = 0 will bring underflow / overflow and DIG_FIFO_ERROR = 1 + * so set it to 1/2 full = 7 before reset as suggested by hardware team. + */ + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); |