diff options
| author | AngeloGioacchino Del Regno <[email protected]> | 2022-07-20 12:28:17 +0200 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2022-08-31 18:16:45 -0700 |
| commit | 3cc53c57d0d54b7fc307879443d555c95b466510 (patch) | |
| tree | 021c2892d59d86d5bf85d8ff9f85722cb1393c1f | |
| parent | 697b551e29b61a00eea46c4704220756587e13af (diff) | |
clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHY
Add the reset idx for the t-phy port 1, used as either USB or
PCI-Express (secondary controller) PHY, depending on board-specific
configuration/layout.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8195-infra_ao.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 75b54ec9c46c..fcd410461d3b 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -200,6 +200,7 @@ static u16 infra_ao_rst_ofs[] = { static u16 infra_ao_idx_map[] = { [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, + [MT8195_INFRA_RST2_USBSIF_P1_SWRST] = 2 * RST_NR_PER_BANK + 18, [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26, [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27, [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, |