diff options
| author | Geert Uytterhoeven <[email protected]> | 2017-01-31 12:17:07 +0100 |
|---|---|---|
| committer | Joerg Roedel <[email protected]> | 2017-02-06 13:09:43 +0100 |
| commit | 3b6bb5b705a4051c9899f5e3100c117c261d2742 (patch) | |
| tree | 5c8929656267dc3dd923112a8a11124fdc050111 | |
| parent | d5adbfcd5f7bcc6fa58a41c5c5ada0e5c826ce2c (diff) | |
iommu/ipmmu-vmsa: Restrict IOMMU Domain Geometry to 32-bit address space
Currently, the IPMMU/VMSA driver supports 32-bit I/O Virtual Addresses
only, and thus sets io_pgtable_cfg.ias = 32. However, it doesn't force
a 32-bit IOVA space through the IOMMU Domain Geometry.
Hence if a device (e.g. SYS-DMAC) rightfully configures a 40-bit DMA
mask, it will still be handed out a 40-bit IOVA, outside the 32-bit IOVA
space, leading to out-of-bounds accesses of the PGD when mapping the
IOVA.
Force a 32-bit IOMMU Domain Geometry to fix this.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Robin Murphy <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Joerg Roedel <[email protected]>
| -rw-r--r-- | drivers/iommu/ipmmu-vmsa.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index ace331da6459..b7e14ee863f9 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -313,6 +313,8 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) domain->cfg.ias = 32; domain->cfg.oas = 40; domain->cfg.tlb = &ipmmu_gather_ops; + domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); + domain->io_domain.geometry.force_aperture = true; /* * TODO: Add support for coherent walk through CCI with DVM and remove * cache handling. For now, delegate it to the io-pgtable code. |