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authorPrajna Rajendra Kumar <[email protected]>2024-05-14 11:45:06 +0100
committerMark Brown <[email protected]>2024-05-27 01:33:14 +0100
commit3b4c0fbc19930af0904fb5995ed4e7b6ffe0b237 (patch)
tree1678ed837f50ab4db163ed34320377f41c52fb5b
parentf44b3730b038363475a3f84bee2038d8b6448ed8 (diff)
spi: dt-bindings: Add num-cs property for mpfs-spi
The PolarFire SoC SPI "hard" controller supports eight CS lines, out of which only one CS line is physically wired. The default value of 'num-cs' was never set and it did not didn't impose a maximum value. To reflect this hardware limitation in the device tree, the binding enforces that the 'num-cs' property cannot exceed 1 unless additional CS lines are explicitly defined using GPIO descriptors. Fixes: 2da187304e55 ("spi: add bindings for microchip mpfs spi") Signed-off-by: Prajna Rajendra Kumar <[email protected]> Link: https://msgid.link/r/[email protected] Reviewed-by: Conor Dooley <[email protected]> Signed-off-by: Mark Brown <[email protected]>
-rw-r--r--Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml29
1 files changed, 26 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index 74a817cc7d94..ffa8d1b48f8b 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -13,9 +13,6 @@ description:
maintainers:
- Conor Dooley <[email protected]>
-allOf:
- - $ref: spi-controller.yaml#
-
properties:
compatible:
oneOf:
@@ -43,6 +40,32 @@ required:
- interrupts
- clocks
+allOf:
+ - $ref: spi-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,mpfs-spi
+ then:
+ properties:
+ num-cs:
+ default: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,mpfs-spi
+ not:
+ required:
+ - cs-gpios
+ then:
+ properties:
+ num-cs:
+ maximum: 1
+
unevaluatedProperties: false
examples: