diff options
| author | Gary Wang <[email protected]> | 2015-08-28 16:40:34 +0800 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2015-08-28 20:32:02 +0300 |
| commit | 39d9b85a4d4fa1642663ca0d208b5c246a3d6f50 (patch) | |
| tree | eea09ddab62b4a401defa651afa1a4fd3f74e42e | |
| parent | 26951caf55d73ceb1967b0bf12f6d0b96853508e (diff) | |
drm/i915: set CDCLK if DPLL0 enabled during resuming from S3
Since BIOS RC 1.4 it would enable CDCLK PLL during BIOS S3 resume, then
driver needs to set CDCLK to avoid display corruption if DPLL0 enabled.
References: https://bugs.freedesktop.org/show_bug.cgi?id=91697
Reviewed-by: Rodrigo Vivi <[email protected]>
Reviewed-by: Damien Lespiau <[email protected]>
Reviewed-by: Cooper Chiou <[email protected]>
Reviewed-by: Wei Shun Chang <[email protected]>
Tested-by: Gary Wang <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Gavin Hindman <[email protected]>
Cc: Chris Wilson <[email protected]>
Cc: Xiong Y Zhang <[email protected]>
Signed-off-by: Gary Wang <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 53f5476bc4bb..8ea9821261ab 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5712,16 +5712,13 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) /* enable PG1 and Misc I/O */ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); - /* DPLL0 already enabed !? */ - if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { - DRM_DEBUG_DRIVER("DPLL0 already running\n"); - return; + /* DPLL0 not enabled (happens on early BIOS versions) */ + if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { + /* enable DPLL0 */ + required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); + skl_dpll0_enable(dev_priv, required_vco); } - /* enable DPLL0 */ - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); - skl_dpll0_enable(dev_priv, required_vco); - /* set CDCLK to the frequency the BIOS chose */ skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); |