diff options
| author | Anshuman Khandual <[email protected]> | 2024-02-20 09:18:29 +0530 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2024-02-21 18:06:54 +0000 |
| commit | 358fee2917058eb06907f966cc69c11ea6c63e1f (patch) | |
| tree | 423db2a93d97112067de6a7932763731dd4749e6 | |
| parent | 7accfaad89d76ca8750da916a242a4ba6a4f83db (diff) | |
arm64/sysreg: Update ID_AA64DFR0_EL1 register
This updates ID_AA64DFR0_EL1.PMSVer and ID_AA64DFR0_EL1.DebugVer register
fields as per the definitions based on DDI0601 2023-12.
Cc: Will Deacon <[email protected]>
Cc: Mark Brown <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Anshuman Khandual <[email protected]>
Reviewed-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Catalin Marinas <[email protected]>
| -rw-r--r-- | arch/arm64/tools/sysreg | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a9cab2b730a3..508224a0e078 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1223,6 +1223,7 @@ UnsignedEnum 35:32 PMSVer 0b0010 V1P1 0b0011 V1P2 0b0100 V1P3 + 0b0101 V1P4 EndEnum Field 31:28 CTX_CMPs Res0 27:24 @@ -1249,6 +1250,7 @@ UnsignedEnum 3:0 DebugVer 0b1000 V8P2 0b1001 V8P4 0b1010 V8P8 + 0b1011 V8P9 EndEnum EndSysreg |