diff options
| author | Alvin Lee <[email protected]> | 2022-05-25 13:34:07 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-06-21 18:17:24 -0400 |
| commit | 32e8ab05ed81c995b92f12b590c12ef951ca1129 (patch) | |
| tree | e584dfccebe79c93f99f3bbd2f19190d4941302f | |
| parent | a3a885878e74d3d81e4742f8dd84faa27c8863ad (diff) | |
drm/amd/display: Update SW state correctly for FCLK
FCLK not supported for DCN321, but still need to update the software
state accordingly to prevent unneeded full updates in driver
Tested-by: Daniel Wheeler <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alvin Lee <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 8ece88ddfb5b..90ba9576a6fb 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -431,12 +431,12 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } - if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && - should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) { + if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) && + clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) { clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; /* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */ - if (!clk_mgr_base->clks.fclk_p_state_change_support) { + if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support) { /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */ dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED); } |