diff options
| author | Matt Roper <[email protected]> | 2023-11-15 10:30:30 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2023-12-21 11:44:38 -0500 |
| commit | 32dd40fb48c56265ab08d379fecb8bbf62e3c427 (patch) | |
| tree | 297bd67666dfefb37ef95fb62d76888d07ca7bd9 | |
| parent | aaa115ffaa467782b01cfa81711424315823bdb5 (diff) | |
drm/xe/dg2: Wa_18028616096 now applies to all DG2
The workaround database was just updated to extend this workaround to
DG2-G11 (whereas previously it applied only to G10 and G12).
Reviewed-by: Gustavo Sousa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Matt Roper <[email protected]>
Signed-off-by: Rodrigo Vivi <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index d03e6674519f..6572715dfc09 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -403,12 +403,7 @@ static const struct xe_rtp_entry_sr engine_was[] = { PERF_FIX_BALANCING_CFE_DISABLE)) }, { XE_RTP_NAME("18028616096"), - XE_RTP_RULES(SUBPLATFORM(DG2, G10), - FUNC(xe_rtp_match_first_render_or_compute)), - XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) - }, - { XE_RTP_NAME("18028616096"), - XE_RTP_RULES(SUBPLATFORM(DG2, G12), + XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) }, |