diff options
| author | Chris Packham <[email protected]> | 2022-08-03 13:16:23 +1200 |
|---|---|---|
| committer | Gregory CLEMENT <[email protected]> | 2022-09-02 16:05:25 +0200 |
| commit | 31be791e26cf928695dba1477d62bbf55854931f (patch) | |
| tree | 686008eeb172241d850069baa18590b27bb50fd1 | |
| parent | 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 (diff) | |
arm64: dts: marvell: Add UART1-3 for AC5/AC5X
The AC5/AC5X SoC has 4 UART blocks. Add the additional UART1-3 blocks to
the base dtsi file.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 80b44c7df56a..914fcf9e2c24 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -95,6 +95,36 @@ status = "okay"; }; + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x11000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + mdio: mdio@22004 { #address-cells = <1>; #size-cells = <0>; |