diff options
| author | Damien Lespiau <[email protected]> | 2014-11-21 16:14:56 +0000 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2014-12-03 09:35:04 +0100 |
| commit | 3148ade72806e7bd1e4784798c2d5645dd13618a (patch) | |
| tree | 37eb8b591f4cef7bd6ee2a8d0a0602b1abad81f0 | |
| parent | 00f0b3781028605910cb4662a0f8a4849b445fc2 (diff) | |
drm/i915/skl: Read out crtl1 for eDP/DPLL0
v2: Put the DPLL0 state readout in skylake_get_ddi_pll(), closer to
where the PLL assignement read out is done rather than the frequency
readout function. (Daniel)
v3: Remove stray new line (Damien)
Add Paulo's r-b tag for v1
Reviewed-by: Paulo Zanoni <[email protected]> (v1)
Signed-off-by: Damien Lespiau <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6289babd03b0..9d38423b69c1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8058,12 +8058,21 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_config *pipe_config) { - u32 temp; + u32 temp, dpll_ctl1; temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); switch (pipe_config->ddi_pll_sel) { + case SKL_DPLL0: + /* + * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part + * of the shared DPLL framework and thus needs to be read out + * separately + */ + dpll_ctl1 = I915_READ(DPLL_CTRL1); + pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; + break; case SKL_DPLL1: pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; break; |